1. Technical Field
The present invention relates to a half voltage generator, and more particularly, to a half voltage generator that generates half voltages used as a cell array power supply in a semiconductor memory device.
2. Description
Half voltages generated by half voltage generators are used as reference voltages for determining the signal quantity of charge in electrodes of a memory cell capacitor of a semiconductor memory device, such as a DRAM, or a precharge voltage for sufficiently charging bit lines or memory cells. In other cases, the half voltages may be used in a semiconductor integrated circuit requiring half voltages. However, as the operating speed of semiconductor integrated circuits is increased and they are more highly integrated, voltage generators that supply half voltages have to generate precise voltages and stably and promptly respond to environmental variations such as changes in production process, voltage, temperature, and load.
FIG. 1 is a circuit diagram illustrating a conventional half voltage generator.
Referring to FIG. 1, a conventional half voltage generator is formed of two resistors R1 and R2, two n-channel metal oxide semiconductor (NMOS) transistors N1 and N2, and two p-channel metal oxide semiconductor (PMOS) transistors P1 and P2. Such a conventional half voltage generator divides a voltage VCCA by using the resistors R1 and R2, and a node voltage between the NMOS transistor N1 and the PMOS transistor P1 drives a push-pull unit comprising the NMOS transistor N2 and the PMOS transistor P2 that has improved driving capacities. Accordingly, the node voltage between the NMOS transistor N1 and the PMOS transistor P1 is copied as an output voltage Vout. When the sizes of the resistances R1 and R2 are the same, the output voltage Vout becomes half (VCCA/2) of the voltage VCCA.
In the conventional half voltage generator of FIG. 1, a bias terminal through which current always flows consumes a large amount of power, and the sizes of the NMOS transistors and the PMOS transistors are increased to drive a large load. Thus, the conventional half voltage generator cannot stably and promptly respond to environmental variations, such as changes in production process, voltage, temperature, and load.
FIG. 2 is a circuit diagram illustrating another conventional half voltage generator.
The conventional half voltage generator in FIG. 2 is formed of a PMOS transistor Rp and an NMOS transistor Rn operating as loads, two NMOS transistors N1 and N2, and two PMOS transistors P1 and P2. In such a conventional half voltage generator, a bias unit comprises the PMOS transistor Rp, the NMOS transistor Rn, the NMOS transistor N1, and the PMOS transistor P1. In the bias unit, the PMOS transistor Rp and the NMOS transistor Rn operate as turn-on resistors. In addition, when the NMOS transistor N1 and the PMOS transistor P1, and the PMOS transistor Rp and the NMOS transistor Rn are symmetrically formed, a node voltage no21 becomes half of the power supply voltage VCCA/2. In this case, a second node voltage no22 and a third node voltage no23 become VCCA/2+Vtn1 and VCCA/2−Vtp1, and such node voltages no22 and no23 drive a push-pull unit comprising the NMOS transistor N2 and the PMOS transistor P2 having improved driving capacities, in order to generate an output voltage Vout. When the NMOS transistor N2 and the PMOS transistor P2 are symmetrically formed, the output voltage Vout becomes half of the power supply voltage VCCA, i.e., it becomes VCCA/2. Here, the voltages Vtn1 and Vtp1 are the threshold voltages of the NMOS transistor N1 and the PMOS transistor P1, respectively. In addition, since the half power supply voltage VCCA/2 and the power supply voltage VCCA are applied to the bulks of the PMOS transistor P1 and the PMOS transistor P2, respectively, and the threshold voltage Vtp1 of the PMOS transistor P1 is smaller than the threshold voltage Vtp2 of the PMOS transistor P2, a current path is not formed in the PMOS transistor P2. Thus, the push-pull terminals N2 and P2 consume a small amount of power. In addition, when the output voltage Vout is changed due to environmental variations, the turn on resistances of the PMOS transistor Rp and the NMOS transistor Rn are changed by a feedback operation in order to maintain the half power supply voltage VCCA/2 as the output voltage Vout.
However, the half voltage generator shown in FIG. 2 consumes a large amount of power and requires large sized NMOS transistors and PMOS transistors to have improved driving capacity. Accordingly, the half voltage generator of FIG. 2 cannot stably and promptly respond to environmental variations, such as changes in production process, voltage, temperature, and load.
The present invention provides a half voltage generator that consumes a small amount of power and stably and promptly responds to environmental variations, such as changes in production process, voltage, temperature, and load.
According to one aspect of the present invention, there is provided a half voltage generator comprising an input buffer unit, a voltage division unit, a current mirror unit, an output buffer unit, and a push-pull driving unit.
Here, the input buffer unit receives a predetermined input voltage and outputs a predetermined control voltage and a predetermined reference voltage using a power supply voltage.
The voltage division unit divides the power supply voltage in half and outputs the half power supply voltage in response to the predetermined control voltage and the predetermined reference voltage.
The current mirror unit receives the predetermined reference voltage and operates as a current mirror.
The output buffer unit is current-limited by current supplied by the current mirror unit, receives the half power supply voltage of the voltage division unit, and outputs the half power supply voltage.
The push-pull driving unit receives the half power supply voltage from the output buffer unit and outputs the half power supply voltage having improved current driving capacity.
According to another aspect of the present invention, there is provided a half voltage generator comprising an input buffer unit, a voltage division unit, a current mirror unit, an even output buffer unit, an odd output buffer unit, an even push-pull driving unit, and an odd push-pull driving unit.
Here, the input buffer unit receives a predetermined input voltage and outputs a predetermined control voltage and a predetermined reference voltage using a power voltage.
The voltage division unit divides the power supply voltage in half and outputs the half power supply voltage in response to the predetermined control voltage and the predetermined reference voltage.
The current mirror unit receives the predetermined reference voltage and operates as a current mirror.
The even output buffer unit, which is limited by current supplied by the current mirror unit, receives the half power supply voltage of the voltage division unit and outputs the half power supply voltage.
The odd output buffer unit receives the half power supply voltage from the voltage division unit and outputs the half power supply voltage.
The even push-pull driving unit receives the output voltage of the even output buffer unit and the output voltage of the odd output buffer unit and outputs the half power supply voltage having improved current driving capacity.
The odd push-pull driving unit receives the output voltage of the even output buffer unit and the output voltage of the odd output buffer unit and outputs the half power supply voltage having the improved current driving capacity.
Beneficially, the predetermined voltage comprises an array reference voltage output from an internal voltage converter (IVC) of a semiconductor memory device.
Beneficially, the input buffer unit comprises a differential amplifier having an NMOS transistor as an input terminal.
Beneficially, the voltage division unit includes more than one PMOS transistor and more than two NMOS transistors that are connected to one another in series, the PMOS transistor is controlled by the predetermined control voltage, the predetermined reference voltage is applied to the gate terminals of more than one NMOS transistor, and the half power supply voltage is output from any one source terminal of the NMOS transistors connected in series. Here, beneficially that the NMOS transistors are low threshold voltage (LTV) NMOS transistors.
Beneficially, the half power supply voltage is applied to gate terminals of more than one NMOS transistor.
Beneficially, the current mirror unit comprises a differential amplifier having an NMOS transistor as an input terminal.
Beneficially, the output buffer unit comprises a differential amplifier having a PMOS transistor as an input terminal.
Beneficially, the push-pull driving unit includes more than one PMOS transistor and more than one NMOS transistor that are connected in series.
Beneficially, the even output buffer unit comprises a differential amplifier having a PMOS transistor as an input terminal, and the odd output buffer unit comprises a differential amplifier having an NMOS transistor as an input terminal.
Beneficially, the even push-pull driving unit or the odd push-pull driving unit includes more than one PMOS transistor and more than one NMOS transistor that are connected in series.
Beneficially, the output of the even output buffer unit drives NMOS gates of the even push-pull driving unit and the odd push-pull driving unit, and the output of the odd output buffer unit drives PMOS gates of the even push-pull driving unit and the odd push-pull driving unit.